The semiconductor industry is rapidly developing chips with smaller and smaller transistor dimensions to gain more functionality per unit area. As the dimensions of devices continue to shrink, so does the gap/space between the devices, increasing the difficulty to physically isolate the devices from one another.
Creating high aspect ratio structures is one of the challenges in the field of device patterning. Many structures in logic and memory benefit from high aspect ratios. Several methods of forming high aspect ratio structure utilize the volumetric expansion of tungsten by oxidation to produce pillars of material around which other materials can be deposited. These tungsten containing pillars are later removed to provide high aspect ratio structures. These structures may later be filled with metallization contacts or other conductive materials.
However, the removal of these tungsten containing pillars often leaves an etch residue. This etch residue may decrease the available volume for any subsequently provided metallization layer and may increase the resistivity of these layers.
Therefore, there is a need in the art for methods of etching metal oxides which produce less etch residue.